Modern enterprise computing environments demand zero-trust isolation anchored directly into physical silicon. AMD Infinity Guard delivers a comprehensive suite of hardware security capabilities built into AMD EPYC™ server and Ryzen™ PRO client processors, safeguarding system memory, execution state, and confidential virtual machines against internal and external threat vectors.
Infinity Guard operates at the lowest levels of the processor hierarchy, isolating control plane hypervisors from tenant workloads through cryptographic boundaries enforced entirely by on-die silicon hardware.
ROOT OF TRUST
A dedicated 32-bit hardware cryptographic coprocessor embedded on the central I/O Die. It manages cryptographic keys, validates initial BIOS execution before x86 cores are released from reset, and executes cryptographic measurements.
MEMORY INTEGRITY
Integrated inline AES-256 hardware memory encryption engines situated between the on-die memory controllers and physical DDR5 DIMM channels. Secures DRAM against physical probing, cold boot attacks, and memory interposer sniffing.
VIRTUALIZATION
Secure Encrypted Virtualization with Secure Nested Paging introduces the Reverse Map Table (RMP). Hardware-enforced page ownership prevents rogue hypervisors from remapping guest pages, tampering with state, or injecting memory replays.
Architectural capability flags and Linux kernel configuration directives across AMD EPYC™ 9005 series server silicon and enterprise hypervisors.
| Hardware Capability | Architectural Protection Boundary | Kernel Parameter | Hardware Verification Target | Minimum Platform |
|---|---|---|---|---|
| Secure Boot Root of Trust | Silicon OTP fuse verification of initial stage firmware | Default ROM | ASP Cryptographic Register | AMD EPYC™ 7002+ |
| Transparent SME (TSME) | Full physical DDR5 memory channel bus encryption | mem_encrypt=on | MSR 0xC0010010 (SYSCFG) | Enterprise BIOS Enable |
| SEV-ES State Encryption | CPU guest register state hashing and hypervisor blinding | kvm_amd.sev=1 | VMSA Page Hash Protection | Linux Kernel 5.15 LTS |
| SEV-SNP Nested Paging | Reverse Map Table (RMP) memory integrity and replay defense | kvm_amd.sev_snp=1 | RMP Hardware Enforcement | Linux Kernel 6.6+ LTS |
| Hardware Shadow Stack (CET) | Return-Oriented Programming (ROP) call stack defense | user_shstk=1 | MSR_IA32_U_CET Register | AMD Zen 4 / Zen 5 |
Cryptographic attestation report binary format emitted by the AMD Secure Processor via the /dev/sev-guest interface to verify enclave integrity.
drivers/virt/coco/sev-guest/sev-guest.h
SPEC REVISION: SEV-SNP ABI 1.55
/* * AMD SEV-SNP Attestation Report Binary Wire Format * Hardware-signed using Versioned Chip Endorsement Key (VCEK) */ struct snp_attestation_report { uint32_t version; /* Report structure version (0x02) */ uint32_t guest_svn; /* Guest Security Version Number */ uint64_t policy; /* Guest execution policy flags */ uint8_t family_id[16]; /* Workload family UUID */ uint8_t image_id[16]; /* Workload deployment hash */ uint32_t vmpl; /* Virtual Machine Privilege Level (0..3) */ uint32_t signature_algo; /* ECDSA P-384 with SHA-384 digest */ platform_version current_tcb; /* Current ASP firmware TCB */ platform_version reported_tcb; /* Reported hardware commitment TCB */ uint8_t platform_info[8]; /* TSME, SMT, and socket configuration */ uint8_t measurement[48]; /* SHA-384 launch digest of guest memory */ uint8_t report_data[64]; /* Caller-provided nonce or public key hash */ uint8_t signature[512]; /* Hardware VCEK cryptographic signature */ };
Global technology organizations utilize AMD Infinity Guard to secure distributed infrastructure, financial transactions, and edge telemetry.
"Deploying AMD EPYC processors with TSME allowed us to enforce end-to-end memory encryption across our commercial fleet telematics without sacrificing edge ingestion throughput."
"By utilizing SEV-SNP hardware attestation, Bullish cryptographically proves that our order-matching engine runs completely untampered within an isolated confidential computing perimeter."
"AMD Infinity Guard provides the verifiable hardware boundaries necessary to detect and prevent double-financing fraud across global banking networks."